In the prior art relating to electronic data processing systems it is known that the speed of operation of the system may be increased by the use of hierarchial memory systems of differing access times. One such system is the cache memory system in which a high speed buffer memory, i.e., the cache memory, is intermediate the requestor, i.e., the central processor unit (CPU), input/output unit (IOU), etc., and the low speed main storage unit (MSU). In the cache memory system of the V. K. Andersen, et al., U.S. Pat. No. 3,967,247, the cache memory system is incorporated in a storage interface unit (SIU) that is intermediate the CPU (requestor) and the MSU. The SIU is adapted to serve as a high speed buffer between the plural requestor units and the relatively low speed MSU in the data processing system. The high speed buffer, i.e., the cache memory, provides temporary storage for a limited number of blocks of data words that are also stored in the MSU.
When access to a particular requestor provided addressable location in the MSU is requested by a requestor, a check is made to determine if that address word is resident in the high speed buffer and if so, it is made available to the requestor for the reading out of or the writing into, i.e., modification or alteration of the data bits. If the desired address word is not resident in the high speed buffer, a block of data words in the high speed buffer is selected for replacement in accordance with a least recently used (LRU) algorithm. When a block of data words is to be displaced from the high speed buffer and a new block of data words is to be requested from the MSU, during the interval that the new block of data words is requested from the MSU the block of data words that is to be displaced is checked for modifications. If any data word of the old block of data words stored in the high speed buffer has been modified since it was originally obtained from the MSU, the entire block of data words is read into a temporary holding register and is restored in or written back into the MSU after the new block of data words has been entered into the high speed buffer at the addressable location vacated by the old block of data words that is to be written back into the MSU.
This operation is called a post-write operation in that the old block of data words that is to be removed from the high speed buffer and that is to be written back into the MSU is temporarily placed within a holding register within the SIU while the new block of data words is read out of the MSU and is stored in the addressable location in the high speed buffer that was vacated by the old block of data words. After the new block of data words has been written into the high speed buffer at the vacated addressable location, the old block of data words, i.e., the least recently used block of data words, is transferred from the holding register into the MSU at the addressable location specified by the address word that was previously stored in the address buffer portion of the cache memory system.
In the post-write operation of the cache memory system, upon readout of the least recently used block of data words from the data buffer portion of the cache memory system and the associated address word from the address buffer portion of the cache memory system, if there is an error in the read out address word, the erroneous address word results in the loss of the readout block of data words, i.e., the address word is in error and therefore the location of the block of data words is unknown. In addition, if the error occurred in the address word during a requestor read operation the erroneous address word, via the SIU, generates a Miss signal even though the correctable desired address word and the associated data word are available in the cache memory system. This erroneously generated Miss signal forces the associated electronic data processing system to undertake various procedures which needlessly occupy otherwise available computational time of the electronic data processing system. Accordingly, it is desirable that a means be provided whereby the number of Miss signals be held to a minimum and that blocks of data words are not lost (when a post-write operation is performed) due to a correctable error in the associated address word. This ensures maximum utilization of the electronic data processing system.